Atlas ZU is a System-On-Module, or SOM, based on the AMD Xilinx Zynq UltraScale+ MPSoC.
The module integrates in a single compact package the Zynq UltraScale+ SoC, LPDDR4 memory, 32 GB eMMC storage, clock generators, a supervisor MCU, and physical interfaces for Ethernet and USB.
The SoC combines a quad-core ARM Cortex-A53 processor, a dual-core ARM Cortex-R5F and UltraScale+ programmable logic, with 4 MGT lanes exported to the carrier board for USB 3.0, DisplayPort and PCIe.
The 200-pin SODIMM form factor (DDR3L standard) keeps the footprint down to 67.6 × 30 mm: all main components are already integrated on the module, simplifying the carrier board architecture. Designers can simply design their own carrier board, plug in Atlas ZU, and start their application development with a proven Zynq UltraScale+ sub-system.
Features
The main component of the Atlas ZU SOM is the AMD Xilinx Zynq UltraScale+ MPSoC (1EG variant). This device combines the ARM Processing System, the UltraScale+ programmable logic and the multi-gigabit transceivers (MGT) in a single chip.
Processing System (PS)
- Quad-core ARM Cortex-A53 @ 1.3 GHz – Application Processing Unit (APU)
- Dual-core ARM Cortex-R5F @ 533 MHz – Real-Time Processing Unit (RPU)
- Integrated Mali-400 MP2 GPU
- DDR/LPDDR4 memory controller with ECC
- USB 3.0 controller with MGT serial PHY (26 MHz reference clock)
- GigE MAC controller (RGMII to PHY on SOM)
- SD/eMMC controller (connected to 32 GB eMMC on SOM)
- JTAG, UART0, UART1 subsystem
Programmable Logic (PL)
- UltraScale+ FPGA fabric – 154K LUT, 141K FF, 7.6 Mb BRAM, 360 DSP
- High-bandwidth AXI interconnect (AXI4, AXI4-Stream, AXI4-Lite)
- MIPI CSI-2 Receiver IP core (D-PHY)
- Video DMA and AXI4-Stream pipeline IP cores
- DisplayPort Tx controller integrated in PS with dedicated MGT lane
MGT resources exported on SODIMM connector
- 4 MGT (Multi-Gigabit Transceiver) lanes exported to the carrier board
- MGT reference clocks: 26 MHz (USB3), 27 MHz (DP), 100 MHz (PCIe) – generated on-SOM
- Maximum lane speed: 6.0 Gbps (XCZU2EG) / 12.5 Gbps (XCZU3EG+)
DOCUMENTS
| Parameter | Value |
| SoC | AMD Xilinx Zynq UltraScale+ MPSoC |
| Variant | 1EG |
| Form factor | SODIMM 200-pin |
| Dimensions | 67.6 × 30 mm |
| CPU (APU) | Quad-core ARM Cortex-A53 @ 1.3 GHz |
| CPU (RPU) | Dual-core ARM Cortex-R5F @ 533 MHz |
| FPGA fabric | UltraScale+ – 154K LUT, 141K FF, 7.6 Mb BRAM |
| RAM memory | LPDDR4 32-bit |
| Onboard storage | eMMC 32 GB |
| USB clock | 26 MHz (dedicated generator) |
| DP clock | 27 MHz (dedicated generator) |
| PCIe clock | 100 MHz (dedicated generator) |
| Supervisor MCU | V/I monitor + watchdog timer |
| GbE PHY | Integrated on SOM (RGMII to carrier board) |
| USB transceiver | Integrated on SOM (MGT lane 2) |
| Carrier connector | SODIMM 200-pin (DDR3L standard) |
Evaluation board
The DVK carrier board supports development with the Atlas module and contains all the peripherals necessary for the management of Gigabit Ethernet, USB, as well as standard interfaces such as uSD card and USB-JTAG programmer.
- USB-C Dual-Role (USB 3.0)
- USB-C JTAG/Console (FTDI)
- DisplayPort (DP 1.x)
- Ethernet GbE (RGMII)
- SD Card
- M.2 PCIe Key-M ×2
- MIPI CSI-2 ZIF 22-pin
- Expansion connectors (diff)
